296 lines
8.0 KiB
Plaintext
296 lines
8.0 KiB
Plaintext
/*
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* Licensed to the Apache Software Foundation (ASF) under one
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* or more contributor license agreements. See the NOTICE file
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* distributed with this work for additional information
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* regarding copyright ownership. The ASF licenses this file
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* to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance
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* with the License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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* KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations
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* under the License.
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*/
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/*------------------ Reference System Memories -------------
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+===================+============+=======+============+============+
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| Memory | Address | Size | CPU Access | NPU Access |
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+===================+============+=======+============+============+
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| ITCM | 0x00000000 | 512KB | Yes (RO) | No |
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+-------------------+------------+-------+------------+------------+
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| DTCM | 0x20000000 | 512KB | Yes (R/W) | No |
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+-------------------+------------+-------+------------+------------+
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| SSE-300 SRAM | 0x21000000 | 2MB | Yes (R/W) | Yes (R/W) |
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+-------------------+------------+-------+------------+------------+
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| Data SRAM | 0x01000000 | 2MB | Yes (R/W) | Yes (R/W) |
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+-------------------+------------+-------+------------+------------+
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| DDR | 0x60000000 | 32MB | Yes (R/W) | Yes (R/W) |
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+-------------------+------------+-------+------------+------------+ */
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/*---------------------- ITCM Configuration ----------------------------------
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<h> Flash Configuration
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<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
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<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__ROM_BASE = 0x00000000;
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__ROM_SIZE = 0x00080000;
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/*--------------------- DTCM RAM Configuration ----------------------------
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<h> RAM Configuration
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<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
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<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__RAM_BASE = 0x20000000;
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__RAM_SIZE = 0x00080000;
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/*----------------------- Data SRAM Configuration ------------------------------
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<h> Data SRAM Configuration
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<o0> DATA_SRAM Base Address <0x0-0xFFFFFFFF:8>
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<o1> DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__DATA_SRAM_BASE = 0x01000000;
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__DATA_SRAM_SIZE = 0x00200000;
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/*--------------------- Embedded SRAM Configuration ----------------------------
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<h> SRAM Configuration
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<o0> SRAM Base Address <0x0-0xFFFFFFFF:8>
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<o1> SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__SRAM_BASE = 0x21000000;
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__SRAM_SIZE = 0x00200000;
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/*--------------------- Stack / Heap Configuration ----------------------------
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<h> Stack / Heap Configuration
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<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__STACK_SIZE = 0x00008000;
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__HEAP_SIZE = 0x00008000;
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/*--------------------- Embedded RAM Configuration ----------------------------
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<h> DDR Configuration
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<o0> DDR Base Address <0x0-0xFFFFFFFF:8>
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<o1> DDR Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__DDR_BASE = 0x60000000;
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__DDR_SIZE = 0x02000000;
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/*
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*-------------------- <<< end of configuration section >>> -------------------
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*/
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MEMORY
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{
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ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
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DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
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DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE
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SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE
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DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions ITCM and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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/* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */
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.ddr :
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{
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. = ALIGN (16);
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*(.rodata.tvm)
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. = ALIGN (16);
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*(.data.tvm);
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. = ALIGN(16);
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} > DDR
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.text :
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{
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KEEP(*(.vectors))
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > ITCM
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > ITCM
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > ITCM
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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/* Add each additional data section here */
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__copy_table_end__ = .;
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} > ITCM
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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__zero_table_end__ = .;
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} > ITCM
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/**
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* Location counter can end up 2byte aligned with narrow Thumb code but
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* __etext is assumed by startup code to be the LMA of a section in DTCM
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* which must be 4byte aligned
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*/
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__etext = ALIGN (4);
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.sram :
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{
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. = ALIGN(16);
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} > SRAM AT > SRAM
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.data : AT (__etext)
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{
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__data_start__ = .;
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*(vtable)
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > DTCM
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.bss.noinit (NOLOAD):
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{
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. = ALIGN(16);
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*(.bss.noinit.*)
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. = ALIGN(16);
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} > SRAM AT > SRAM
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.bss :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > DTCM AT > DTCM
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.data_sram :
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{
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. = ALIGN(16);
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} > DATA_SRAM
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.heap (COPY) :
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{
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. = ALIGN(8);
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__end__ = .;
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PROVIDE(end = .);
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. = . + __HEAP_SIZE;
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. = ALIGN(8);
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__HeapLimit = .;
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} > DTCM
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.stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
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{
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. = ALIGN(8);
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__StackLimit = .;
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. = . + __STACK_SIZE;
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. = ALIGN(8);
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__StackTop = .;
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} > DTCM
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PROVIDE(__stack = __StackTop);
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/* Check if data + stack exceeds DTCM limit */
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ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack")
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}
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