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faiss/docs/html/search/classes_69.js

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Initial commit
2017-02-23 06:26:44 +08:00
var searchData=
[
['idselector',['IDSelector',['../structfaiss_1_1IDSelector.html',1,'faiss']]],
['idselectorbatch',['IDSelectorBatch',['../structfaiss_1_1IDSelectorBatch.html',1,'faiss']]],
['idselectorrange',['IDSelectorRange',['../structfaiss_1_1IDSelectorRange.html',1,'faiss']]],
['index',['Index',['../structfaiss_1_1Index.html',1,'faiss']]],
['indexflat',['IndexFlat',['../structfaiss_1_1IndexFlat.html',1,'faiss']]],
['indexflat1d',['IndexFlat1D',['../structfaiss_1_1IndexFlat1D.html',1,'faiss']]],
['indexflatip',['IndexFlatIP',['../structfaiss_1_1IndexFlatIP.html',1,'faiss']]],
['indexflatl2',['IndexFlatL2',['../structfaiss_1_1IndexFlatL2.html',1,'faiss']]],
['indexflatl2baseshift',['IndexFlatL2BaseShift',['../structfaiss_1_1IndexFlatL2BaseShift.html',1,'faiss']]],
['indexidmap',['IndexIDMap',['../structfaiss_1_1IndexIDMap.html',1,'faiss']]],
['indexivf',['IndexIVF',['../structfaiss_1_1IndexIVF.html',1,'faiss']]],
['indexivfflat',['IndexIVFFlat',['../structfaiss_1_1IndexIVFFlat.html',1,'faiss']]],
Better support for low-mem GPUs avoid reading beyond the end of an array in fvec_L2sqr and related functions
2017-04-06 19:33:41 +08:00
['indexivfflatipbounds',['IndexIVFFlatIPBounds',['../structfaiss_1_1IndexIVFFlatIPBounds.html',1,'faiss']]],
['indexivfflatstats',['IndexIVFFlatStats',['../structfaiss_1_1IndexIVFFlatStats.html',1,'faiss']]],
Initial commit
2017-02-23 06:26:44 +08:00
['indexivfpq',['IndexIVFPQ',['../structfaiss_1_1IndexIVFPQ.html',1,'faiss']]],
['indexivfpqcompact',['IndexIVFPQCompact',['../structfaiss_1_1IndexIVFPQCompact.html',1,'faiss']]],
['indexivfpqr',['IndexIVFPQR',['../structfaiss_1_1IndexIVFPQR.html',1,'faiss']]],
['indexivfpqstats',['IndexIVFPQStats',['../structfaiss_1_1IndexIVFPQStats.html',1,'faiss']]],
Synchronization with FB version 2017-06-21 * moved most FAISS_ASSERT calls to C++ exceptions, and adjusted memory allocation to avoid mem leaks * added an IndexIVFScalarQuantizer type that offers an intermediate compression between IVFFlat and IVFPQ * support removal of indices in IndexIDMap / IndexFlat combination * various fixes in GPU code
2017-06-21 21:54:28 +08:00
['indexivfscalarquantizer',['IndexIVFScalarQuantizer',['../structfaiss_1_1IndexIVFScalarQuantizer.html',1,'faiss']]],
Initial commit
2017-02-23 06:26:44 +08:00
['indexlsh',['IndexLSH',['../structfaiss_1_1IndexLSH.html',1,'faiss']]],
['indexpq',['IndexPQ',['../structfaiss_1_1IndexPQ.html',1,'faiss']]],
['indexpqstats',['IndexPQStats',['../structfaiss_1_1IndexPQStats.html',1,'faiss']]],
['indexpretransform',['IndexPreTransform',['../structfaiss_1_1IndexPreTransform.html',1,'faiss']]],
['indexproxy',['IndexProxy',['../classfaiss_1_1gpu_1_1IndexProxy.html',1,'faiss::gpu']]],
['indexrefineflat',['IndexRefineFlat',['../structfaiss_1_1IndexRefineFlat.html',1,'faiss']]],
['indexshards',['IndexShards',['../structfaiss_1_1IndexShards.html',1,'faiss']]],
['indexsplitvectors',['IndexSplitVectors',['../structfaiss_1_1IndexSplitVectors.html',1,'faiss']]],
['indexwrapper',['IndexWrapper',['../structfaiss_1_1gpu_1_1IndexWrapper.html',1,'faiss::gpu']]],
['indirectsort',['IndirectSort',['../structfaiss_1_1IndirectSort.html',1,'faiss']]],
['intersectioncriterion',['IntersectionCriterion',['../structfaiss_1_1IntersectionCriterion.html',1,'faiss']]],
['inttolong',['IntToLong',['../structfaiss_1_1gpu_1_1IntToLong.html',1,'faiss::gpu']]],
['ivfbase',['IVFBase',['../classfaiss_1_1gpu_1_1IVFBase.html',1,'faiss::gpu']]],
['ivfflat',['IVFFlat',['../classfaiss_1_1gpu_1_1IVFFlat.html',1,'faiss::gpu']]],
['ivfflatscan',['IVFFlatScan',['../structfaiss_1_1gpu_1_1IVFFlatScan.html',1,'faiss::gpu']]],
['ivfflatscan_3c_200_2c_20l2_2c_20t_20_3e',['IVFFlatScan< 0, L2, T >',['../structfaiss_1_1gpu_1_1IVFFlatScan_3_010_00_01L2_00_01T_01_4.html',1,'faiss::gpu']]],
['ivfflatscan_3c_20128_2c_20l2_2c_20float_20_3e',['IVFFlatScan< 128, L2, float >',['../structfaiss_1_1gpu_1_1IVFFlatScan_3_01128_00_01L2_00_01float_01_4.html',1,'faiss::gpu']]],
['ivfflatscan_3c_20256_2c_20l2_2c_20float_20_3e',['IVFFlatScan< 256, L2, float >',['../structfaiss_1_1gpu_1_1IVFFlatScan_3_01256_00_01L2_00_01float_01_4.html',1,'faiss::gpu']]],
['ivfflatscan_3c_2064_2c_20l2_2c_20float_20_3e',['IVFFlatScan< 64, L2, float >',['../structfaiss_1_1gpu_1_1IVFFlatScan_3_0164_00_01L2_00_01float_01_4.html',1,'faiss::gpu']]],
['ivfflatscan_3c_2d1_2c_20l2_2c_20t_20_3e',['IVFFlatScan<-1, L2, T >',['../structfaiss_1_1gpu_1_1IVFFlatScan_3-1_00_01L2_00_01T_01_4.html',1,'faiss::gpu']]],
['ivfpq',['IVFPQ',['../classfaiss_1_1gpu_1_1IVFPQ.html',1,'faiss::gpu']]]
];