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Summary: This PR adds a new architecture mode to support the new extensions to AVX512, namely [AVX512-FP16](https://networkbuilders.intel.com/solutionslibrary/intel-avx-512-fp16-instruction-set-for-intel-xeon-processor-based-products-technology-guide), which have been available since Intel® Sapphire Rapids. This PR is a prerequisite for [PR#4020](https://github.com/facebookresearch/faiss/pull/4020) that speeds up hamming distance evaluations. Pull Request resolved: https://github.com/facebookresearch/faiss/pull/4025 Reviewed By: pankajsingh88 Differential Revision: D67524575 Pulled By: mengdilin fbshipit-source-id: f3a09943b062d720b241f95aef2f390923ffd779
24 lines
309 B
Plaintext
24 lines
309 B
Plaintext
*.swp
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*.swo
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*.o
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*.a
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*.dSYM
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*.so
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*.dylib
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*.pyc
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*~
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/build/
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/config.*
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/aclocal.m4
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/autom4te.cache/
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/makefile.inc
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/bin/
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/c_api/bin/
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/c_api/gpu/bin/
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/tests/test
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/tests/gtest/
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faiss/python/swigfaiss_avx2.swig
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faiss/python/swigfaiss_avx512.swig
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faiss/python/swigfaiss_avx512_spr.swig
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faiss/python/swigfaiss_sve.swig
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