Summary:
related: https://github.com/facebookresearch/faiss/issues/2884
This PR contains below changes:
- Add new optlevel `sve`
- ARM SVE is _extension_ of ARMv8, so it should be treated similar to AVX2 IMO
- Add targets for ARM SVE, `faiss_sve` and `swigfaiss_sve`
- These targets will be built when you give `-DFAISS_OPT_LEVEL=sve` at build time
- Design decision: Don't fix SVE register length.
- The python package of faiss is "fat binary" (for example, the package for avx2 contains `_swigfaiss_avx2.so` and `_swigfaiss.so`)
- SVE is scalable instruction set (= doesn't fix vector length), but actually we can specify the vector length at compile time.
- [with `-msve-vector-length=` option](https://developer.arm.com/documentation/101726/4-0/Coding-for-Scalable-Vector-Extension--SVE-/SVE-Vector-Length-Specific--VLS--programming)
- When this option is specified, the binary can't work correctly on the CPU which has other vector length rather than specified at compile time
- When we use fixed vector length, SVE-supported faiss python package will contain 7 shared libraries like `_swigfaiss.so` , `_swigfaiss_sve.so` , `_swigfaiss_sve128.so` , `_swigfaiss_sve256.so` , `_swigfaiss_sve512.so` , `_swigfaiss_sve1024.so` , and `_swigfaiss_sve2048.so` . The package size will be exploded.
- For these reason, I don't specify the vector length at compile time and `faiss_sve` detects the vector length at run time.
- Add a mechanism of detecting ARM SVE on runtime environment and importing `swigfaiss_sve` dynamically
- Currently it only supports Linux, but there is no SVE environment with non-Linux OS now, as far as I know
NOTE: I plan to make one more PR about add some SVE implementation after this PR merged. This PR only contains adding sve target.
Pull Request resolved: https://github.com/facebookresearch/faiss/pull/2886
Reviewed By: ramilbakhshyiev
Differential Revision: D60386983
Pulled By: mengdilin
fbshipit-source-id: 7e66162ee53ce88fbfb6636e7bf705b44e6c3282
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